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Cadenti
logic family
medium scale integration
metal oxide semiconductor
ac register
accumulator logic
adder circuit
basic computer design
branch unconditionally
flowchart
input and output communication
input output instruction
input register
interrupt cycle
logic adder circuits
logic gates
output register
register and memory
binary code
binary number
clock pulse
data types
decimal numbers
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NAND implementation
A sum-of-products expression can be implemented with NAND gates as shown in Fig. 1-13(a). Note that the second NAND gate is drawn with the graphic symbol of Fig. 1-5(b). There are three lines in the diagram with small circles at both ends. Two circles in the same line designate double complementation, and since (x')' = x, the two circles can be removed and the resulting diagram is equivalent to the one shown in Fig. 1-12(a).

Figure 1-5

Figure 1-12