• Cadenti
  logic family
  medium scale integration
  metal oxide semiconductor
  ac register
  accumulator logic
  adder circuit
  basic computer design
  branch unconditionally
  flowchart
  input and output communication
  input output instruction
  input register
  interrupt cycle
  logic adder circuits
  logic gates
  output register
  register and memory
  binary code
  binary number
  clock pulse
  data types
  decimal numbers
  

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Control unit

The block diagram of the control unit is shown in Fig. 5-6. It consists of two decoders, a sequence counter, and a number of control logic gates. An instruction read from memory is placed in the instruction register (IR). The position of this register in the common bus system is indicated in Fig. 5-4. The instruction register is shown again in Fig. 5-6, where it is divided into three parts: the I bit, the operation code, and bits 0 through 11. The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight outputs of the decoder are designated by the symbols Do through D7. The subscripted decimal number is equivalent to the binary value of the corresponding operation code. Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I. Bits 0 through 11 are applied to the control logic gates. The 4-bit sequence counter can count in binary from 0 through 15.

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