cadenti index

Global Business Resources
Find out worldwide manufacturers and traders.
Discover best resources in global-business-resource.com.
business services.

Modified fetch phase

We now modify the fetch and decode phases of the instruction cycle.

Instead of using only timing signals To, Tlr and T2 we will AND the three timing signals with R' so that the fetch and decode phases will be recognized from the three control functions R'T0, R'TU and R'T2. The reason for this is that after the instruction is executed and SC is cleared to 0, the control will go through a fetch phase only if R = 0. Otherwise, if R = 1, the control will go through an interrupt cycle. The interrupt cycle stores the return address (available in PC) into memory location 0, branches to memory location 1, and clears IEN, R, and SC to 0. This can be done with the following sequence of microoperations:

RT0: ARâ†0, TRâ†PC

RTi. M[AR]â†TR, PCâ†0

RT2: PCâ†PC + 1, IENâ†0, Râ†0, SCâ†0

During the first timing signal AR is cleared to 0, and the content of PC is transferred to the temporary register TR. With the second riming signal, the return address is stored in memory at location 0 and PC is cleared to 0. The third timing signal increments PC to 1, clears IEN and R, and control goes back to To by clearing SC to 0. The beginning of the next instruction cycle has the condition R'T0 and the content of PC is equal to 1. The control then goes through an instruction cycle that fetches and executes the BUN instruction in location 1.