• Cadenti
  logic family
  medium scale integration
  metal oxide semiconductor
  ac register
  accumulator logic
  adder circuit
  basic computer design
  branch unconditionally
  flowchart
  input and output communication
  input output instruction
  input register
  interrupt cycle
  logic adder circuits
  logic gates
  output register
  register and memory
  binary code
  binary number
  clock pulse
  data types
  decimal numbers
  

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Control Flowchart

A flowchart showing all microoperations for the execution of the seven memory-reference instructions is shown in Fig. 5-11. The control functions are indicated on top of each box. The microoperations that are performed during time T4, T5, or T6 depend on the operation code value. This is indicated in the flowchart by six different paths, one of which the control takes after the instruction is decoded. The sequence counter SC is cleared to 0 with the last timing signal in each case. This causes a transfer of control to timing signal To to start the next instruction cycle.

Figure 5-11

Note that we need only seven timing signals to execute the longest instruction (ISZ). The computer can be designed with a 3-bit sequence counter. The reason for using a 4-bit counter for SC is to provide additional timing signals for other instructions that are presented in the problems section.

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