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Incrementer

 The diagram of a 4-bit combinational circuit incrementer is shown in Fig. 4-8. One of the inputs to the least significant half-adder (HA) is connected to logic-1 and the other input is connected to the least significant bit of the number to be incremented. The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-adder. The circuit receives the four bits from Ao through A3, adds one to it, and generates the incremented output in So through S3. The output carry C4 will be 1 only after incrementing binary 1111. This also causes outputs So through S3 to go to 0.

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