• Cadenti
  logic family
  medium scale integration
  metal oxide semiconductor
  ac register
  accumulator logic
  adder circuit
  basic computer design
  branch unconditionally
  flowchart
  input and output communication
  input output instruction
  input register
  interrupt cycle
  logic adder circuits
  logic gates
  output register
  register and memory
  binary code
  binary number
  clock pulse
  data types
  decimal numbers
  

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Load(LD)

 The particular  register whose LD (load) input is enabled receives the data from the bus during the next clock pulse transition. The memory receives the contents of the bus when its write input is activated.

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