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Cadenti
logic family
medium scale integration
metal oxide semiconductor
ac register
accumulator logic
adder circuit
basic computer design
branch unconditionally
flowchart
input and output communication
input output instruction
input register
interrupt cycle
logic adder circuits
logic gates
output register
register and memory
binary code
binary number
clock pulse
data types
decimal numbers
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Multiplexers
A multiplexer is a combinational circuit that receives binary information from one of 2" input data lines and directs it to a single output line. The selection of a particular input data line for the output is determined by a set of selection inputs. A 2"-to-1 multiplexer has 2" input data lines and n input selection lines whose bit combinations determine which input data are selected for the output.
Figure 2-4
A 4-to-l-line multiplexer is shown in Fig. 2-4. Each of the four data inputs Io through 13 is applied to one input of an AND gate. The two selection inputs S, and So are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate to provide the single output. To demon strate the circuit operation, consider the case when SlSo = 10. The AND gate associated with input 12 has two of its inputs equal to 1. The third input of the gate is connected to 12. The other three AND gates have at least one input equal to 0, which makes their outputs equal to 0. The OR gate output is now equal to the value of 12, thus providing a path from the selected input to the output. The 4-to-1 line multiplexer of Fig. 2-4 has six inputs and one output. A truth table describing the circuit needs 64 rows since six input variables can have 26 binary combinations. This is an excessively long table and will not be shown here. A more convenient way to describe the operation of multiplexers is by means of a function table. The function table for the multiplexer is shown in Table 2-3. The table demonstrates the relationship between the four data inputs and the single output as a function of the selection inputs Sl and So. When the selection inputs are equal to 00, output Y is equal to input lo. When the selection inputs are equal to 01, input 1, has a path to output Y, and similarly for the other two combinations.
Table 2-3
