• Cadenti
  logic family
  medium scale integration
  metal oxide semiconductor
  ac register
  accumulator logic
  adder circuit
  basic computer design
  branch unconditionally
  flowchart
  input and output communication
  input output instruction
  input register
  interrupt cycle
  logic adder circuits
  logic gates
  output register
  register and memory
  binary code
  binary number
  clock pulse
  data types
  decimal numbers
  

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Parity checker

At the receiving end, all the incoming bits (in this case, four) are applied to a parity checker that checks the proper parity adopted (odd or even). An error is detected if the checked parity does not conform to the adopted parity. The parity method detects the presence of one, three, or any odd number of errors. An even number of errors is not detected.

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