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Cadenti
logic family
medium scale integration
metal oxide semiconductor
ac register
accumulator logic
adder circuit
basic computer design
branch unconditionally
flowchart
input and output communication
input output instruction
input register
interrupt cycle
logic adder circuits
logic gates
output register
register and memory
binary code
binary number
clock pulse
data types
decimal numbers
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Subroutine call
The BSA instruction performs the function usually referred to as a sub- routine call. The indirect BUN instruction at the end of the subroutine performs the function referred to as a subroutine return. In most commercial computers, the return address associated with a subroutine is stored in either a processor register or in a portion of memory called a stack.
It is not possible to perform the operation of the BSA instruction in one clock cycle when we use the bus system of the basic computer. To use the memory and the bus properly, the BSA instruction must be executed with a sequence of two microoperations:
D5T4: M[AR]âPC, ARâAR + 1
D5T5: PC â AR, SC â 0
Timing signal T4 initiates a memory write operation, places the content of PC onto the bus, and enables the INR input of AR. The memory write operation is completed and AR is incremented by the time the next clock transition occurs. The bus is used at T5 to transfer the content of AR to PC.